1. Field of the Invention
The present invention relates to an apparatus and method for displaying test results, and to a recording medium, and in particular, to an apparatus and method for displaying results of a test in which each of a plurality of semiconductor chips formed on a wafer substrate is tested, and to a recording medium on which a display program is recorded.
2. Description of the Prior Art
Conventionally, for example, a predetermined voltage is applied to each of the semiconductor chips formed on a wafer substrate to carry out a test (a probe test or the like) to check whether memories and devices formed on the semiconductor chips are operating in a normal state by checking whether a predetermined voltage value which the chip was designed to exhibit is in fact detected when the predetermined voltage is applied to the semiconductor chips. In this way, the quality of the chips (memories and devices) is checked.
At this time, as shown in FIG. 6, numbers (1-7) indicative of the results of the test of the chips are displayed on a screen in correspondence with the each of positions of the semiconductor chips on the wafer substrate. At the same time, the number of semiconductor chips detected as having a given value (one of 1-7) is displayed on the screen for each of the detected values. These numbers (1-7) indicate the quality level of the semiconductor chips. For example, the number 1 denotes a good quality, 2 denotes a quality that can be made good through a very simple correction processing, 3 denotes a quality that can be made good through a relatively simple correction processing, 4 denotes a quality that can be made good through a complicated correction processing, 5 denotes a device failure (defective device), 6 denotes a memory failure, and 7 denotes a function failure. The quality level is determined every time in accordance with the test contents and the test results.
By summing up such quality level, the quality level (failure level) in which the detected number of the semiconductor chips is large is clarified. The causes of the failure are investigated and the results of the investigation are fed back to the manufacturing step for the prevention of failures for the same reason the next time the product is manufactured.
Generally, in testing semiconductor chips, a wafer prober or the like is used which has a tester having a plurality of groups of probes which are each a test portion for testing one semiconductor chip. The wafer prober is used to carry out parallel measurement for testing a plurality of semiconductor chips at the same time, thereby shorting the test time.
For example, there will be considered a case of a wafer prober in which a tester having sixteen groups of probes arranged in eight rows and two columns is provided. The semiconductor chips formed on the wafer substrate are positioned in rows and columns as shown in FIG. 7. As shown in FIG. 7, the tester is disposed at a test start reference position (the slanted line region of FIG. 7). In the case where a semiconductor chip corresponding to at least one of the sixteen groups of probes of the tester is present, the semiconductor chip is tested by the group of probes corresponding thereto. When the test by the groups of probes is completed, the tester is shifted two rows, and a test region 40 is shifted by two rows. When a semiconductor chip is present which corresponds to at least one of the probes, the semiconductor chip is tested with the group of probes corresponding thereto. When testing of all the semiconductor chips formed at the positions of rows one to eight on the wafer substrate is completed by repeating the aforementioned process, the tester is returned to the test start reference position and is shifted eight columns. Thereafter, testing of the semiconductor chips formed at the positions of rows nine to sixteen on the wafer substrate is carried out as described above.
By repeating such operations, all of the 536 semiconductor chips formed on one wafer substrate are tested by the movement of the tester 48 times (carrying out testing 48 times).
Shortening of the test time is important in terms of improving manufacturing efficiency. Conventionally, there has been proposed a wafer prober that is capable of moving the tester freely in order to carry out testing in a short time. As shown in FIG. 8, there is proposed a system in which the test region 40 can be set in correspondence with the configuration of a disc-shaped wafer substrate by moving the tester along the configuration of the disc-like wafer substrate so that the number of times testing is carried out by the tester is decreased.
In the example shown in FIG. 7, all of the 536 semiconductor chips are tested by carrying out testing 48 times. However, by moving the tester in accordance with the configuration of the disc-shaped wafer substrate, it becomes possible to test all of the 536 semiconductor chips in 44 tests. The time required for testing can thus be shortened by the amount of time required for four tests.
Since the semiconductor chips are very small and the electrodes formed on the semiconductor chips are also considerably minute, the probe for applying voltage to the semiconductor chips by contacting the electrode of the chip is also extremely small. As a result, the probe is liable to be broken if a load is applied to the probe during the movement of the tester, or the probe gets caught on the edge of the wafer substrate.
Accurate test results cannot be obtained from damaged probes. Thus, even a good quality semiconductor chip which is subjected to testing may be detected as being a poor product. Such incorrect test results are unfavorable. Therefore, it is necessary to detect at an early stage the fact that the probe has been damaged, so that adjustments to the semiconductor test device can be made and the test instruments can be checked with a view to restoring normal operation in a short time.
Conventionally, when results of testing the semiconductor chip (the quality levels of the semiconductor chips) are displayed on the screen in correspondence to the positions of the semiconductor chips on the substrate, the relative position of the probe with respect to the tester (hereinafter referred to as DFT (Device For Testing)) is displayed on the screen in an overlaid manner on the test results of the semiconductor chips on the monitor, so that the operator can detect the damage caused to the probe as soon as possible.
With a wafer prober in which the movement of the tester is restricted, for example, as shown in FIG. 7, since each of the DFT's is shifted (arranged) along the same column on the wafer substrate, the damage on the probe can be detected relatively easily. However, in a case where testing is carried out by using a wafer prober in which the tester is moved freely, for example, as shown in FIG. 8, the respective DFT's are not necessarily shifted along the same column on the wafer substrate. Thus, it is difficult to detect at an early stage which of the DFT's is damaged.
Furthermore, in recent years, owing to the smaller sizing resulting from the shrinkage or the like of the semiconductor chips and an increase in the diameter of the wafer substrate, the number of chips which can be formed on a single wafer substrate has become very large. As a result, it becomes difficult to display on one screen of the monitor the test results for one wafer substrate. Therefore, only a portion of the test results for one wafer substrate is displayed on one screen of the monitor. For this reason as well, it is difficult to correspond each of the semiconductor chips being tested by the one of the DFT's with each of the DFT's, and thus, it becomes difficult to detect at an early stage which of the probes of the DFT are damaged.